NoC Emulation - 2021.1 English

Versal ACAP System Integration and Validation Methodology Guide (UG1388)

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2021.1 English

NoC emulation support is provided with behavioral models in either SystemVerilog (RTL in GUI) or SystemC (TLM in GUI). The simulation time with the SystemC model is much faster but is cycle approximate and less accurate compared to the SystemVerilog model.

Although you can use both the SystemC and SystemVerilog models to verify functionality, the SystemVerilog model is recommended for performance analysis. Performance analysis using the SystemVerilog model is within ±5% of hardware.

You can emulate the NoC using simulators in the Vivado tools or using the hardware emulation flow provided by the Vitis environment.

Important: For more information the NoC simulation settings and performance tuning, see this link and this link in the Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).