Step 6: Saving Power using UltraScale Block RAM in Cascaded Mode - 2020.2 English

UltraScale architecture-based devices provide the capability to cascade the data out from one block RAM to the next block RAM serially. This will enable the devices to create a deeper block RAM in a bottom-up fashion. When used in cascaded mode, the power consumption is considerably low compared to the block RAM used in non-cascaded mode.

1. Run the steps mentioned in Step 1 shown in Lab 1.
   1. In the Add Source Files dialog box, navigate to the

      <Extract_Dir>/UltraScale/src for UltraScale devices.

   2. In the Add Constraints (optional) dialog box, click Add Files and select dut_fpga_kcu105.xdc in the file browser. In the directory structure, you will find the dut_fpga_kcu105.xdc file below the /src folder.
   3. Select the Kintex UltraScale KCU105 Evaluation Platform (xcku040-ffva156-2-e FPGA), click Next.
2. Review the New Project Summary page. Verify that the data appears as expected and click Finish.
3. In the Vivado Options dialog box (Tools > Options > General), enter the tutorial project directory in the Specify project directory box, so that all reports are saved in the tutorial project directory. Then click OK.
4. Click Run Synthesis in the Flow Navigator.

   The Synthesis Completed dialog box appears after synthesis has completed on the design.

5. Select Run Implementation in the Synthesis Completed dialog box and click OK.
6. After the Implementation completes, click Open Implemented Design.
7. You can see the automatically generated power report impl_1 in the power tab, which shows as a saved report. This is an autogenerated vectorless power report.
8. Note the total power (Total On-Chip Power) in the power report Summary page.
   
   
9. Select Hierarchical view in the Utilization Details option on the left panel and observe the Cascaded and Non-cascaded block RAM power.
   
   
10. You can see 50% to 60% saving in Cascaded block RAM compared to Non Cascaded block RAM.
11. Use the same steps as specified in Step 1, Step 2, and Step 3 to perform SAIF based power analysis using Vivado Simulator.