Assume the reset is asserted for 10% of the cycles in this design. Switching activity can be set accordingly to re-estimate the power.
- In the Net Properties window, click the Edit Properties button.
- In the Edit Power Properties dialog
box, change the Toggle
rate to 4% and the Static
probability to 0.1.
- Click OK.
- In the Net
Properties window, observe that the Toggle Rate and Static Probability values turn a
different color to indicate that they are user defined.
You can also observe the equivalent Tcl command executed in the Tcl Console.
- Rerun Report Power ( ).
- Change the Output text File and Output XPE File in the Output tab to power_2.pwr and power_2.xpe respectively.
- In the Switching tab, set Switching Activity for Resets: to None. Then click OK.
- In the Power
window, note the change in total power reported in the power_2 report compared
to the power_1 report. The total power has decreased due to the change in the
Signal Rate for the
dut/dut_reset
signal. Because the signal is a reset signal, an increase in its activity will significantly reduce the activity of other signals in the design. The Signal Rate of thedut/dut_reset
signal is now color coded as being User Defined in both the properties window and the Set/Reset view of the Power Report.You can also observe the equivalent Tcl command executed in the Tcl Console.
Xilinx recommends you to double-check the signal rates and percentage high (%high) values of high impact I/O ports, control signals (such as resets and clock enables) and high fanout nets. This is an opportunity to guide the Report Power tool to the right estimation scenario.
See the Vivado Design Suite User Guide: Power Analysis and Optimization (UG907) for more information on switching activity.
set_switching_activity
command to change the signal
rate and static probability of signals and use report_switching_activity
to query the values that were set on the
signals.set_switching_activity -signal_rate 4 -static_probability 0.1 [get_nets dut/dut_reset]
report_switching_activity [get_nets dut/dut_reset]
set_input_delay
and set_output_delay
commands. If no clock association is found, Report
Power will associate
the ports with respect to the capturing clock.For a clock of 100 MHz and a toggle rate of 4, the equivalent signal rate will be 4 MTr/s (signal_rate = toggle_rate * Freq = 4 * 100 MHz ).