Generating a SAIF File using Questa Advanced Simulator - 2020.2 English

Vivado Design Suite Tutorial: Power Analysis and Optimization (UG997)

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2020.2 English

The following steps will take you through the process of SAIF file creation, running timing simulation, and estimating power using the SAIF data using Questa Advanced Simulator.

Important: Make sure the Vivado Design Suite knows where to pick up the Questa Advanced Simulator tool. You can either:

Manually set the path to ModelSim/Questa Advanced Simulator using the $PATH environment variable


From the Tools > Settings > Tool Settings section, define the path to the simulator in the Vivado IDE under the 3rd Party Tools tab: Questa Advanced Simulator install path.

Make sure the Compiled library location points to a valid location for the compiled Xilinx simulation libraries.

To create new compiled libraries:

  1. In the 3rd Party Simulators tab, specify the Compiled library location to Questa Advanced Simulator. Use the Compiled library location specified during the compiled library generation and enter it in the Compiled library location field of the 3rd Party Simulators tab. It should point to the compile_simlib directory.
  2. Click OK to define the path and generate compiled libraries.