For details, see the Vivado Design Suite User Guide: Designing with IP (UG896).
Note: When the CAM IP is generated, a simulation SystemVerilog package file
is also created with the name <instance-name>_sim_pkg.sv.
This file contains the SystemVerilog task
create which contains the
configuration settings used for this particular CAM IP instance. You can use this
simulation package file and thus the SystemVerilog tasks in it in their own
testbench if desired.