IP Facts - 2.2 English

Semi-Ternary CAM Search LogiCORE IP Product Guide (PG319)

Document ID
Release Date
2.2 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 UltraScale+™ , UltraScale™ , Zynq® UltraScale+™ , Versal™ ACAP
Supported User Interfaces AXI4-Stream and AXI4-Lite Interfaces
Resources See the CAM Configuration section in the Main Tab topic.
Provided with Core
Design Files Encrypted Verilog RTL
Example Design Verilog
Test Bench Verilog
Constraints File Xilinx Design Constraint (XDC)
Simulation Model Verilog source code
Supported S/W Driver 2 Standalone
Software Example Design Application Standalone, Vivado® IP integrator
Tested Design Flows 3
Design Entry 4 Standalone, VitisNetP4, Vivado® IP integrator.
Simulation 5 For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Xilinx Vivado Synthesis
Release Notes and Known Issues Master Answer Record: N/A
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado® IP catalog.
  2. Standalone driver details can be found online.
  3. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.
  4. The CAM IP is only supported in the Vivado IP Catalog running on a Linux operating system (not supported on Windows).
  5. Modelsim, Questa, VCS, Xcelium, and Xsim are supported. Refer to Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973) for information on version compatibility.