- Associative array containing arbitrary (key, mask, priority, response) entries.
- Ternary match key lookup returns hit/miss result and associated response value on hit.
- High throughput: one lookup per clock cycle at 600 MHz.Note: Achievable clock frequencies will depend on the device being used, the resources used by the CAM configuration, and the congestion in the device.
- Flexible, supports a wide range of key widths, response widths and lookup rates with optimized resource utilization.
- Supports all key widths up to 991 bits and all response widths up to 1024 bits.
- Up to eight 16-bit wide range comparison fields in each rule minimizes the need for costly rule expansion.
- Supports both UltraRAM (URAM) and block RAM implementations.
- Scalable, supports one or multiple TCAM instances, each instance can use all UltraRAM / block RAM within an SLR allowing for very large TCAMs.
- Supports error correction coding (ECC). Single-bit errors are corrected dynamically during lookups, and permanently with patrol scrubbing.
- Supports Vivado® IP integrator.
- Supports entry insert, delete, update using standard TCAM-like software APIs.
- Can be inferred from within P4 code using the Vitis Networking P4 (VitisNetP4) tool.