Resource Utilization - 1.1 English - PG389

DPUCVDX8G for Versal ACAPs Product Guide (PG389)
Document ID
PG389
Release Date
2022-01-20
Version
1.1 English

The resource utilization of several DPUCVDX8G architectures is shown in the following table. The C32 means that the CPB_N (number of AI Engine cores per batch handler) is 32. The C64 means that the CPB_N=64. B3 means that there are three batch handlers, and L2S2 means that there are 2 HP interfaces per batch handler for loading and saving images between DPUCVDX8G and NOC.

Table 1. Referenced Resources Utilization of Different DPUCVDX8G Architectures
Architecture AIE Cores LUT FF Block RAM UltraRAM DSP PL NMU
C32B1L2S2 32 81130 110290 0 204 139 8
C32B2L2S2 64 143298 188293 0 268 273 10
C32B3L2S2 96 205300 266294 0 332 407 12
C32B4L2S2 128 267712 344287 0 396 541 14
C32B5L2S2 160 331760 424086 0 460 675 16
C32B6L2S2 192 394740 502056 644 411 809 18
C64B1L2S2 64 92006 131532 0 204 139 8
C64B2L2S2 128 154845 213640 0 268 273 10
C64B3L2S2 192 217780 295732 0 332 407 12
C64B4L2S2 256 281268 378567 0 396 541 14
C64B5L2S2 320 348671 464122 0 460 675 16