IP Facts - 1.1 English

DPUCVDX8G for Versal ACAPs Product Guide (PG389)

Document ID
Release Date
1.1 English
DPUCVDX8G IP Facts Table
Core Specifics
Supported Device Family Versal® AI Core Series
Supported User Interfaces AXI4-Lite, AXI4-Stream
Resources See Resource Utilization
Provided with Core
Design Files Encrypted RTL and Encrypted AIE kernel code
Example Design Verilog
Test Bench Not Provided
Constraints File Xilinx Constraints File
Simulation Model Not Provided
Supported S/W Driver Included in PetaLinux
Tested Design Flows 1
Design Entry Vitis™ Unified Software Platform
Simulation N/A
Synthesis Vivado® Synthesis
Xilinx Support web page
  1. For the supported versions of third-party tools, see the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).