次の表に、 Vivado® IDE のフィールドとユーザー パラメーターの対応関係を示します。ユーザー パラメーターは Tcl コンソールで表示できます。
| Vivado IDE のパラメーター | ユーザー パラメーター | デフォルト値 |
|---|---|---|
|
[Bus Direction]
|
BUS_DIR | 0 |
[BiDir Mode]
|
BIDIR_MODE | 1 |
| [Enable BIDIR state machine] 範囲:
注記: このオプションは、BIDIR または BIDIR 混合モードの場合のみ利用できます。
|
EN_BIDIR_SM | 0 |
|
[Interface Speed (Mb/s)] 範囲: 200 ～ 1800Mb/s 注記: この範囲は、次の選択によって変わります。
|
DATA_SPEED | 1000 |
|
[PLL Clk Input Frequency (MHz)] 範囲: 100 ～ 1099MHz 注記: この範囲は、スピード グレードによって変わります。
|
INPUT_CLK_FREQ | 500.00 |
|
[Clock Data Relation (RX Strobe)] 範囲:
|
CLK_TO_DATA_ALIGN | 4 |
|
[PLL Clock Source] 範囲:
|
PLL_CLK_SOURCE | BUFG_TO_PLL |
|
[Enable Custom CDR] 範囲:
|
ENABLE_CUSTOM_CDR | 0 |
|
[TX/RX Serialization Factor] 範囲: 2、4、8 |
TX/RX_SERIALIZATION_FACTOR | 8 |
|
[Serialization Factor] 範囲: 2、4、8 |
SERIALIZATION_FACTOR | 8 |
|
[Select if PLL is included in core or Example Design] 範囲:
|
PLL_IN_CORE | 0 |
|
[Forwarded Clock Phase (TX Signal Type = Clk Fwd)] 範囲:
|
CLK_FWD_PHASE | 0 |
|
[Single IO Std] 範囲: デバイスによって異なる |
SINGLE_IO_STD | なし |
|
[Differential IO Std] 範囲: デバイスによって異なる |
DIFFERENTIAL_IO_STD | なし |
|
[RIU Interface] 範囲:
|
ENABLE_RIU_INTERFACE | 0 |
|
[Enable Simple RIU] 範囲:
|
SIMPLE_RIU | 0 |
|
[Enable BitSlip] 範囲:
|
ENABLE_BITSLIP | 0 |
|
[Enable Data Bitslip] 範囲:
|
ENABLE_DATA_BITSLIP | 0 |
|
[3-state]
|
DATA_TRISTATE | 1 |
| [Number of Channels] | BUS<0-16>_NUM_PINS | 1 |
| [Signal Name] | BUS<0-16>_SIG_NAME | Data_pins_0 |
|
[Pin Direction]
|
BUS<0-16>_DIR | None |
|
[Signal IO Type]
|
BUS<0-16>_IO_TYPE | SINGLE |
| [Signal Type] | BUS<0-16>_SIG_TYPE | Data |
| [Enable Strobe] | BUS<0-16>_STROBE_EN | FALSE |
| [Strobe Name] | BUS<0-16>_STROBE_NAME | Strobe_0 |
| [Enable WrClk] | BUS<0-16>_WRCLK_EN | FALSE |
| [WrClk Name] | BUS<0-16>_WRCLK_NAME | WrClk_0 |
|
[Strobe IO Type]
|
BUS<0-16>_STROBE_IO_TYPE | SINGLE |
|
[WrClk IO Type]
|
BUS<0-16>_WRCLK_IO_TYPE | SINGLE |
|
[Application Data Width] 範囲: 4、8 |
APPLICATION_DATA_WIDTH | 8 |
|
[Application] 範囲:
|
APPLICATION_TYPE | SOURCE_SYNCHRONOUS |
|
[FIFO_WRCLK_OUT] 範囲:
|
PLL_FIFO_WRITE_CLK_EN | FALSE |
|
[Reduce Control Signal] 範囲:
|
REDUCE_CONTROL_SIG_EN | FALSE |
|
[IOB Power Saving] 範囲:
|
ENABLE_IOB_POWER_SAVING | FALSE |
| [IOB Power Control] 範囲:
|
IOB_POWER_CONTROL | User Controlled |
| [Enable Delay Control Signals] 範囲:
|
DELAY_CTRL_SIG_EN | FALSE |
| [ENABLE CDR DEBUG SIGNALS] 範囲:
|
ENABLE_CDR_DEBUG | FALSE |
| [Enable BLI Logic] 範囲:
|
ENABLE_BLI | TRUE |
| [Enable Debug Ports] 範囲:
|
ENBALE_DEBUG_PORTS | FALSE |
| [Enable ILA in Example Design] 範囲:
|
ENABLE_ILA_IN_EXDES | FALSE |
| [Multi Banks are Part of a Triplet] 範囲:
|
BANKS_IN_TRIPLET | FALSE |
|
[FIFO MODE enablement] 範囲:
|
FIFO_MODE_EN_GUI | FALSE |
|
[FIFO Mode Options] 範囲:
|
FIFO_MODES | ASYNC |
|
[FIFO Read Enable User Control] 範囲:
|
FIFO_RD_EN_CTRL | FALSE |
| [Strobe Selection (For PLL Input)] 範囲:
|
STROBE_SEL | 0 |
| [PACKAGE] | PACKAGE | 0.0 |
| [CHANNEL] | CHANNEL | 0.0 |
|
||