• Xilinx programming
° Fully automated in-line ATE flow at Xilinx test house
° Secure programming for medium to high volumes – with uniform settings
• Avnet programming
° Opportunities for security, handling, serialization, and other differentiators
° Ideal for programming from moderate volumes, down through low volumes
• Customer manufacturing flow
° Third-party tool, or integrated in design (XAPP1283) [Ref 7] , using Xilinx programming technology
° Ideal for custom requirements including highly-secret information handling
RECOMMENDED:
For the eFUSE solution it is also recommended to take the following precautions for in-system programming of the AES key:
-Prevent or clear the FPGA of a configured design to minimize power supply noise within the FPGA.
-If possible, stop board-level system clocks to minimize system power supply noise.
After connection to a valid HW target using Vivado Hardware Manager, right-click the UltraScale FPGA to allow selection of either Program BBR Key... or Program eFUSE Registers... depending on which storage option you have previously selected (see This Figure ).
