Buffering Requirements - 1.0 English

AXI4-Stream Video IP and System Design Guide (UG934)

Document ID
UG934
Release Date
2022-11-16
Version
1.0 English

The output interface module does not start generating valid output frames until it receives valid data on its input AXI4-Stream interface. However, after periodic output frame generation starts, all cores in the processing pipeline should be able to provide data at the rate required by the output standard.

For most output standards three different data rates should be defined. As an example, 720p30 video over DVI rates are used. Table: Output Data Rates describes the three data rates.

Table 3-6: Output Data Rates

Pixel Rate

Description

Active

Within the active portion of each row, pixels are sent back to back on each clock cycle, at 37.125 MHz.

Line

Active video lines typically contain active and non-active (horizontally blanked) periods. As no pixels need to be transmitted in the non-active period, the average data rate within an active line is less than the active pixel rate. For 720p30 over DVI, this rate is 28.8 Mega-samples per second (Msps).

Frame

Video frames typically contain active, and non-active (vertically blanked) periods. As no pixels need to be transmitted in the non-active period, the average data rate within a frame is less than line pixel rate. For 720p30 over DVI, this rate is 27.648 Msps.

Identifying the above rates helps determine what type of buffering is necessary, if any, within or between processing cores. If a processing core can maintain the active pixel rate indefinitely, such as a test-pattern generator core, no buffering is necessary.

If a processing core cannot maintain the active pixel rate but can maintain the line pixel rate, a line buffer is necessary on the processing core output.

If a processing core cannot maintain the line pixel rate but can maintain the frame pixel rate, a frame buffer is necessary on the processing core output. It is assumed that the frame buffer IP also contains line buffers to smooth access bursts.

If a processing core cannot maintain the frame pixel rate due to insufficient throughput, no amount of buffering is sufficient to produce uninterrupted output video for the desired output standard.