Creating a Memory IP Customization - 2024.1 English

Vivado Design Suite User Guide: Designing with IP (UG896)

Document ID
UG896
Release Date
2024-05-30
Version
2024.1 English

The Memory IP creates memory controllers for AMD devices and IP. Memory IP creates complete customized RTL source code, pinout, and design constraints for the selected FPGA, and script files for implementation and simulation.

In 7 series devices, memory IP is referred to as Memory Interface Generator (MIG). This terminology is deprecated with the AMD UltraScale™ and UltraScale+ devices. See the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150), and Zynq 7000 SoC and 7 series Devices Memory Interface Solutions (UG586) for more information.

For memory IP on the AMD Zynq™ UltraScale+™ MPSoC processor, the Vivado tools launch a pin planning project, and lets you set the appropriate pins for that device. See the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).

Video: See the Vivado Design Suite QuickTake Video: Designing with UltraScale Memory IP for instructions on how to use memory IP.

The Designing with IP Design Hub in the AMD Document Navigator provides videos and links to Memory IP documentation.