[Figure 1, callout 17]
The VCU128 board includes a Silicon Labs Si5328B jitter attenuator U87 on the back side of the board. FPGA U1 bank 67 implements two QSFP RX differential clocks (QSFP1_RECCLK_P, pin BH26 and QSFP1_RECCLK_N, pin BH25, and QSFP2_RECCLK_P, pin BJ26 and QSFP2_RECCLK_N, pin BK25) for jitter attenuation.
The jitter attenuated clock pair (SI5328_CLOCK1_C_P (U87 output pin 28), SI5328_CLOCK1_C_N (U87 output pin 29) is routed as a reference clock to FPGA U1 QSFP2 I/F GTY Quad 134 inputs MGTREFCLK1P (U1 pin R40) and MGTREFCLK1N (U1 pin R41).
The jitter attenuated clock pair (SI5328_CLOCK2_C_P (U87 output pin 35), SI5328_CLOCK2_C_N (U87 output pin 34) is routed as a reference clock to FPGA U1 QSFP3 I/F GTY Quad 132 inputs MGTREFCLK1P (U1 pin W40) and MGTREFCLK1N (U1 pin W41).
The primary purpose of this clock is to support synchronous protocols, such as common packet radio interface (CPRI) or open base station architecture initiative (OBSAI). These synchronous protocols perform clock recovery from user-supplied QSFP/QSFP+ modules, and use the jitter attenuated recovered clock to drive the reference clock inputs of a GTY transceiver.
The jitter attenuated clock circuit is shown in the following figure.
The SI5328B U87 I2C interface is connected to port 1 of the I2C0 bus TCA9548A U53 bus switch and can be configured by either the U42 system controller or U1 FPGA IP.
The system controller configures SI5328B U87 in free-run mode or automatically switches over to one of two recovered clock inputs for synchronous operation. Enabling the jitter attenuation feature requires additional user programming through the I2C bus. The Silicon Labs Si570 and Si5328B data sheets are available on the Silicon Labs website.