Analyze the Current Constraints Files - 2024.1 English

Vivado Design Suite Tutorial: Creating and Packaging Custom IP (UG1119)

Document ID
UG1119
Release Date
2024-06-19
Version
2024.1 English
  1. In the Hierarchy view of the Sources window, open the target XDC file (uart_top.xdc) under the Constraints folder, as shown in the following figure:

    There are two items to take note of in the XDC file, as seen above.

    • create_clock constraints (lines 1 and 2)
    • set_max_delay constraint relying on the clock object period value (line 14).
    Note: The line numbers referenced in the preceding figure might differ from the line numbers in your XDC file because the constraints were edited for easier viewing in this tutorial.
  2. Examine all create_clock constraints prior to packaging the new IP definition.

    If the created clock is internal to the IP (GT), or if the IP contains an input buffer (IBUF), the create_clock constraint should stay in the IP XDC file because it is necessary to define local clocks.

    In the next sub-step, you move clocks that are not internal, or local, to the IP from the IP XDC file to an OOC XDC file, because the parent design provides the clock.

    For this example, you move the create_clock constraints on line 1 and 2 from the design XDC file to an OOC XDC file. When you instantiate the IP you are packaging from the IP catalog into a design, the IP inherits the clock definitions from the parent design.

    The set_max_delay constraint is also noteworthy in that it has a dependency on the PERIOD property of defined clocks (get_clocks –of_objects). This dependency is affected by the order of processing of the constraints of the IP and top-level design.

    By default, when IP customizations are instantiated into a design, the AMD Vivado™ IDE processes the XDC files of an IP before the XDC files of the top-level design. This is known as EARLY processing, and is defined by the PROCESSING_ORDER property on the XDC file.

    By default, the XDC files of the top-level design are marked for NORMAL processing. This means that the processing of XDC files for IP constraints happens before the top-level design constraints created by the user.

    In the case of the set_max_delay constraint, the dependency on the clock PERIOD causes errors in processing the IP constraints early and defining the clock later.

    To resolve this issue, mark the XDC files of the UART IP for LATE processing.
    Tip: AMD delivered IP with _clock appended to the XDC filename are all marked for LATE processing.