IP Facts - 1.1 English

DPUCVDX8H for Convolutional Neural Networks Product Guide (PG403)

Document ID
Release Date
1.1 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family VCK5000
Supported User Interfaces AXI4-Lite CSR Interface
Resources See Performance and Resource Use
Provided with Core
Design Files XO files/connection files/AIE library file
Example Design Verilog
Constraints File Xilinx Design Constraints (XDC)
Supported S/W Driver XRT
Tested Design Flows 1
Design Entry Vivado® Design Suite
Simulation N/A
Synthesis Vivado Synthesis
  1. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.