XPM_CDC_PULSE - 1.0 English

MACRO_GROUP: XPM
MACRO_SUBGROUP: XPM_CDC

Introduction

This macro synchronizes a pulse in the source clock domain to the destination clock domain. A pulse of any size in the source clock domain, if initiated correctly, generates a pulse the size of a single destination clock period.

For proper operation, the input data must be sampled two or more times by the destination clock. You can define the number of register stages used in the synchronizers. An optional source and destination reset can be used to reset the pulse transfer logic. You can also enable a simulation feature to generate messages which report any potential misuse of the macro.

The implementation of this macro requires some feedback logic. When simulating the macro without the optional reset signals, the input pulse signal (src_pulse) must always be defined because there is no reset logic to recover from an undefined or ‘x’ propagating through the macro.

This macro also requires the following minimum gap between subsequent pulse inputs:

2*(larger(src_clk period, dest_clk period))

The minimum gap is measured between the falling edge of a src_pulse to the rising edge of the next src_pulse. This minimum gap will guarantee that each rising edge of src_pulse will generate a pulse the size of one dest_clk period in the destination clock domain.

When using the optional reset signals, src_rst and dest_rst_in must be asserted simultaneously for at least the following duration to fully reset all the logic in the macro:

((DEST_SYNC_FF+2)*dest_clk_period) + (2*src_clk_period)

When reset is asserted, the input pulse signal should not toggle and the output pulse signal is not valid and should be ignored.

The following waveform demonstrates how to reset the macro and transfer back-to-back pulses while abiding the minimum gap between each pulse.

Figure 1. Timing for Macro and Transfer Back-to-Back Pulses

Port Descriptions

Table 1. Port Descriptions
Port	I/O	Width	Domain	Sense	Handling if Unused	Function
dest_clk	I	1	N/A	EDGE _RISING	Active	Destination clock.
dest_pulse	O	1	dest_clk	LEVEL _HIGH	Active	Os a pulse the size of one dest_clk period when a pulse transfer is correctly initiated on src_pulse input. This output is combinatorial unless REG_OUTPUT is set to 1.
dest_rst_in	I	1	dest_clk	LEVEL _HIGH	0	Unused when RST_USED = 0. Destination reset signal if RST_USED = 1. Resets all logic in destination clock domain. To fully reset the macro, src_rst and dest_rst_in must be asserted simultaneously for at least ((DEST_SYNC_FF+2)dest_clk_period) + (2src_clk_period).
src_clk	I	1	N/A	EDGE _RISING	Active	Source clock.
src_pulse	I	1	src_clk	EDGE _RISING	Active	Rising edge of this signal initiates a pulse transfer to the destination clock domain. The minimum gap between each pulse transfer must be at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured between the falling edge of a src_pulse to the rising edge of the next src_pulse. This minimum gap will guarantee that each rising edge of src_pulse will generate a pulse the size of one dest_clk period in the destination clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while src_rst and/or dest_rst_in are asserted.
src_rst	I	1	src_clk	LEVEL _HIGH	0	Unused when RST_USED = 0. Source reset signal if RST_USED = 1. Resets all logic in source clock domain. To fully reset the macro, src_rst and dest_rst_in must be asserted simultaneously for at least ((DEST_SYNC_FF+2)dest_clk_period) + (2src_clk_period).

Design Entry Method

Table 2. Design Entry Method
Design Entry	Yes/No
Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	Yes

Available Attributes

Table 3. Available Attributes
Attribute	Type	Allowed Values	Default	Description
DEST_SYNC_FF	DECIMAL	2 to 10	4	Number of register stages used to synchronize signal in the destination clock domain.
INIT_SYNC_FF	DECIMAL	0, 1	0	0: Disable behavioral simulation initialization value(s) on synchronization registers. 1: Enable behavioral simulation initialization value(s) on synchronization registers.
REG_OUTPUT	DECIMAL	0, 1	0	0: Disable registered output 1: Enable registered output
RST_USED	DECIMAL	1, 0	1	0: No resets implemented. 1: Resets implemented. When RST_USED = 0, src_pulse input must always be defined during simulation because there is no reset logic to recover from an x-propagating through the macro.
SIM_ASSERT_CHK	DECIMAL	0, 1	0	0: Disable simulation message reporting. Messages related to potential misuse will not be reported. 1: Enable simulation message reporting. Messages related to potential misuse will be reported.