- Ingress-side and Egress-side AXI4-Stream interfaces:
- 1024-bit segmented AXI4-Stream interface for 400G port (8x128-bit segments)
- 512-bit segmented AXI4-Stream interface per 200G port (4x128-bit segments)
- 256-bit segmented AXI4-Stream interface per 100G port (2x128-bit segments)
- Double-wide 512-bit segmented AXI4-Stream interface per 100G port (4x128-bit segments) which supports half-frequency clock for use in low power devices
- AXI4-Lite interface to access the control and statistics registers