Block-based registers are organized in to a series of 16-byte blocks, which align with the HSC Subsystem cipher data-block and AXIS segment size. Each 16-byte block consists of 4*4-byte registers, exactly like the Word-based Registers. A series of blocks is grouped together to create a RAM-like structure in registers. Examples include:
- CAVP_TX_ENC_REQ_TXT_REG
- CAVP_TX_ENC_REQ_TXT_REG_0
- CAVP_TX_ENC_REQ_TXT_REG_0_LSB
- CAVP_TX_ENC_REQ_TXT_REG_0_MID1
- CAVP_TX_ENC_REQ_TXT_REG_0_MID2
- CAVP_TX_ENC_REQ_TXT_REG_0_MSB3
- ...
- CAVP_TX_ENC_REQ_TXT_REG_9
- CAVP_TX_ENC_REQ_TXT_REG_9_LSB
- CAVP_TX_ENC_REQ_TXT_REG_9_MID1
- CAVP_TX_ENC_REQ_TXT_REG_9_MID2
- CAVP_TX_ENC_REQ_TXT_REG_9_MSB3
- CAVP_TX_ENC_REQ_TXT_REG_0
- CAVP_TX_ENC_RESP_TXT_REG
- CAVP_TX_ENC_RESP_TXT_REG_0
- CAVP_TX_ENC_RESP_TXT_REG_0_LSB
- CAVP_TX_ENC_RESP_TXT_REG_0_MID1
- CAVP_TX_ENC_RESP_TXT_REG_0_MID2
- CAVP_TX_ENC_RESP_TXT_REG_0_MSB3
- ...
- CAVP_TX_ENC_RESP_TXT_REG_9
- CAVP_TX_ENC_RESP_TXT_REG_9_LSB
- CAVP_TX_ENC_RESP_TXT_REG_9_MID1
- CAVP_TX_ENC_RESP_TXT_REG_9_MID2
- CAVP_TX_ENC_RESP_TXT_REG_9_MSB3
- CAVP_TX_ENC_RESP_TXT_REG_0
- CAVP_RX_DEC_REQ_TXT_REG
- CAVP_RX_DEC_REQ_TXT_REG_0
- CAVP_RX_DEC_REQ_TXT_REG_0_LSB
- CAVP_RX_DEC_REQ_TXT_REG_0_MID1
- CAVP_RX_DEC_REQ_TXT_REG_0_MID2
- CAVP_RX_DEC_REQ_TXT_REG_0_MSB3
- ...
- CAVP_ RX_DEC_REQ_TXT_REG_9
- CAVP_RX_DEC_REQ_TXT_REG_9_LSB
- CAVP_RX_DEC_REQ_TXT_REG_9_MID1
- CAVP_RX_DEC_REQ_TXT_REG_9_MID2
- CAVP_RX_DEC_REQ_TXT_REG_9_MSB3
- CAVP_RX_DEC_REQ_TXT_REG_0
- CAVP_ RX_DEC _RESP_TXT_REG
- CAVP_RX_DEC_RESP_TXT_REG_0
- CAVP_RX_DEC_RESP_TXT_REG_0_LSB
- CAVP_RX_DEC_RESP_TXT_REG_0_MID1
- CAVP_RX_DEC_RESP_TXT_REG_0_MID2
- CAVP_RX_DEC_RESP_TXT_REG_0_MSB3
- ...
- CAVP_RX_DEC_RESP_TXT_REG_9
- CAVP_RX_DEC_RESP_TXT_REG_9_LSB
- CAVP_RX_DEC_RESP_TXT_REG_9_MID1
- CAVP_RX_DEC_RESP_TXT_REG_9_MID2
- CAVP_RX_DEC_RESP_TXT_REG_9_MSB3
- CAVP_RX_DEC_RESP_TXT_REG_0
The HSC Subsystem expects the most-significant bytes to be provided first in an AXI4-Stream transaction, and similarly provides the most-significant bytes first on egress. Moreover, the HSC Subsystem expects the AAD portion of the data to be provided before the plain/cipher text portion of the data. The HSC Subsystem provides data on egress in the same way.
- Concatenate the AAD (if any) and PT/CT (if any) values from the vector:
{AAD,PT/CT}. - Pad with 0’s as needed on the right to create an even number of 16-byte blocks.
- Break
{AAD,PT/CT,0-PAD}in to 16-byte blocks. - Write the leftmost block to CAVP_TX_ENC_REQ_TXT_REG_0 (CAVP_RX_DEC_REQ_TXT_REG_0) by following the procedure in Word-based Registers.
- Write the next leftmost block to CAVP_TX_ENC_REQ_TXT_REG_1 (CAVP_RX_DEC_REQ_TXT_REG_1) by following the procedure in Word-based Registers.
- Continue until all blocks have been written.
The HSC Subsystem request logic byte-swaps the text from register 0
and provides it first in the AXI4-Stream transaction. Register 1 is
byte-swapped and provided second, and so on. This sequence provides the most-significant
byte first to the HSC Subsystem. Padding bytes at the end are
excluded by setting the enc/dec_igr_axis_tuser_mty<M> (M = 0, 1, …,
7) signals to mark the empty (pad) bytes at EOP.
The HSC Subsystem response logic byte-swaps the first segment of data from the AXI4-Stream transaction and places it in register 0. The second segment of data is byte-swapped and placed in register 1, and so on. This sequence puts the data in the expected format for the CAVP vectors.
- Read the CAVP_*_RESP_TXT_REG_0 register by following the procedure in Word-based Registers.
- Read the CAVP_*_RESP_TXT_REG_1 register by following the procedure in Word-based Registers.
- Concatenate the read values as
{REG_0, REG_1}. - Continue until all blocks have been read to create
{AAD,PT/CT,0-PAD}(i.e., the same format as writes above). - Extract the appropriate number bytes for AAD, PT/CT, and 0-PAD from the vector.
The following figure shows an example of writing the text registers for Encryption. Reading is the same, but in reverse.
