Core
Specifics |
Supported Device Family
1
|
Virtex®
UltraScale+™
with
HBM |
Supported User Interfaces |
AXI4 on Slave side AXI3 on Master side |
Resources |
Resource Use
|
Provided with Core
|
Design Files |
Encrypted RTL |
Example Design |
Provided |
Test Bench |
Verilog |
Constraints File |
Not Provided |
Simulation Model |
Not Provided |
Supported S/W Driver |
Not Applicable |
Tested Design Flows
2
|
Design Entry |
Vivado® Design Suite
|
Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
Synthesis |
Vivado®
Synthesis |
Support |
Release Notes and Known
Issues |
Master Answer Record: 69267
|
All Vivado IP Change Logs |
Master Vivado
IP Change Logs: 72775
|
Xilinx
Support web page
|
- For a complete list of supported devices, see
the Vivado IP catalog.
- For the supported versions of third-party
tools, see the Xilinx Design Tools: Release Notes
Guide.
|