Constraining the Core - 1.1 English

RAMA 1.1 LogiCORE IP Product Guide (PG310)
Document ID
PG310
Release Date
2021-01-21
Version
1.1 English

Required Constraints

This section is not applicable for this IP core.

Device, Package, and Speed Grade Selections

All Xilinx® UltraScale+™ devices with High Bandwidth Memory (HBM) can use RAMA IP.

Clock Frequencies

AXI_ACLK has a nominal frequency of 450 MHz. A lower clock frequency may be used, with the consequence that HBM access efficiency would be reduced.

Clock Management

This section is not applicable for this IP core.

Clock Placement

This section is not applicable for this IP core.

Banking

This section is not applicable for this IP core.

Transceiver Placement

This section is not applicable for this IP core.

I/O Standard and Placement

This section is not applicable for this IP core.