Example Design Hierarchy (GT in Example Design) - 1.2 English

When the USXGMII Ethernet subsystem is added to AMD Vivado™ IP integrator, the Run Block Automation IP/Core and GT (Serial transceivers) will get connected with some helper blocks as per the core configuration. There is a reset interface IP, internal to USXGMII Ethernet IP, used to release TX/RX mstreset to the Versal device GT and check for TX/RX mstresetdone status and reset sequencing to GT.

Figure 1. Single Core with GT in Example Design Hierarchy

Figure 2. Single Core with GT in Example Design Hierarchy (Versal Adaptive SoC)

The previous figures show the instantiation of various modules and their hierarchy for a single core configuration of the usxgmii_0 example design when the GT (serial transceiver) is outside the core, that is, it is in the example design. This hierarchical example design is delivered when you select the Include GT subcore in example design option from the GT Selection and Configuration tab.

The usxgmii_0_core_support.v is present in the hierarchy when you select the Include GT subcore in example design option from the GT Selection and Configuration tab or the Include Shared Logic in example design option from the Shared Logic tab. This instantiates the usxgmii_0_sharedlogic_wrapper.v module and the usxgmii_0.v module for the Include Shared Logic in example design option. The usxgmii_0_gt_wrapper.v module will be present when you select the GT subcore in example design option.

The user interface available is the same as mentioned in Core Overview.

The usxgmii_0.v module instantiates the necessary the sync registers/retiming pipeline registers for the synchronization of data between the core and the GT.

The usxgmii_0_pkt_gen_mon module is used to generate the data packets for sanity testing. The packet generation and checking is controlled by a Finite State Machine (FSM) module.

Description of optional modules are as follows:

• usxgmii _0_sharedlogic_wrapper: this module is present in the example design when you select the Include GT subcore in example design option from the GT Selection and Configuration tab or Include Shared Logic in the Example Design from the Shared Logic tab. This module brings all modules that can be shared between multiple IP cores and designs outside the core.

• usxgmii_0_gt_wrapper: this module is present in the example design when you select the Include GT subcore in example design option from the GT Selection and Configuration tab. This module has instantiations of the GT along with various helper blocks. The clocking helper blocks are used to generate the required clock frequency for the core.

The following figure shows the instantiation of various modules and their hierarchy for the multiple core configuration of the usxgmii_0 example design when the GT is in the example design.

Figure 3. Multiple Core with GT in Example Design Hierarchy (UltraScale/UltraScale+)

For Versal platforms, the gt_quad_base (GT Wizard for Versal device) are a part of the example design only, and USXGMII Ethernet Subsystem IP and GT (Serial transceiver) IP are connected in the block design using the IP integrator.

The following figure is a block design, where USXGMII Ethernet example design is connected in the IP integrator. See the Vivado Design Suite Tutorial: Designing IP Subsystems Using IP Integrator (UG995) for more information on IP integrator.

Figure 4. USXGMII Ethernet Block Design