• AXI4 Compliant
• Primary AXI4 data width support of 32, 64, 128, 256, 512, and 1,024 bits
• Primary AXI4-Stream data width support of 8, 16, 32, 64, 128, 256, 512 and 1,024 bits
• Parameterized Memory Map Burst Lengths of 2, 4, 8, 16, 32, 64, 128, and 256 data beats
•
Optional Unaligned Address access;
Up to 64 bit address support.
• Optional General Purpose Store-And-Forward in both Memory Map to Stream (MM2S) and Stream to Memory Map (S2MM)
• Optional Indeterminate Bytes to Transfer (BTT) mode in S2MM
• Supports synchronous/asynchronous clocking for Command/Status interface
Core Specifics |
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Supported Device Family (1) |
UltraScale+™ UltraScale™ Zynq®-7000 SoC 7 Series FPGAs |
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Supported User Interfaces |
AXI4, AXI4-Stream |
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Resources |
See Table: 7 Series and Zynq-7000 Device Resource Estimates and Table: UltraScale Device Resource Estimates . |
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Provided with Core |
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Design Files |
VHDL |
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Example Design |
VHDL |
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Test Bench |
VHDL |
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Constraints File |
Delivered during IP generation |
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Simulation Model |
Not Provided |
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Supported
|
N/A |
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Tested Design Flows (2) |
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Design Entry |
Vivado® Design Suite |
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Simulation |
For supported simulators, see the |
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Synthesis |
Not Provided |
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Support |
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Release Notes and Known Issues |
Master Answer Record: 47651 |
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All Vivado IP Change Logs |
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Notes: 1. For a complete list of supported devices, see the Vivado IP catalog.
2.
For the supported versions of the tools, see the
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