Introduction - 1.4 English

High-Speed Transceiver Pin Multiplexing IP LogiCORE IP Product Brief (PB074)

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1.4 English

The High-Speed Transceiver Pin Multiplexing (HSTPM) IP core provides a low latency solution for off-chip connectivity over Xilinx® Gigabit Transceiver (GTs). For emulation and prototyping use cases, the off-chip connectivity needs to be cycle accurate. The HSTPM IP core provides multilane GT connectivity between the devices. The data transmitted over the HSTPM core can be cycle accurate with a synchronized reference clock.

Figure 1. Blocks and Status