- User data width from 32 to 8192 bits (excluding UltraFast mode):
- UltraFast mode in 32-bit phy mode provides 32-bit user data width.
- UltraFast mode in 64-bit phy mode provides 64-bit user data width.
- Selectable number of lanes per quad from 1 to 16 (depending on quad topology).
- Adjustable line rate (in Gb/s):
- 0.5 Gb/s to 28 Gb/s (GTY -3 devices).
- Reference clock options depending on selected line rates.
- Selectable GT locations:
- Overwritable locations with XDC constraints.
- User configurable master lane, in case of multi lane mode.
- Dynamic reconfiguration port (DRP) common:
- Post implementation line rate change.
- PCS/PMA loopback for characterization and design bringup.