76908 - Vivado 2021.1 Vivado Versal Clocking : Deskew logic for MMCM and DPLL are timed incorrectly

Release Date

Designs using the MMCM’s deskew logic should be retimed with the 2021.1 patch (or upgraded to the 2021.2 version of the tools) to ensure that the design is meeting timing. If there are any timing failures, the design should be re-implemented.

Designs using off-chip feedback must use the MMCM with the CLKFBIN for the feedback delays to be correctly calculated.

Note: (Xilinx Answer) and (Xilinx Answer 76848) share a common patch for ease of use which is attached to Vivado 2021.1.x - Versal Clock Calibrated Deskew Timing issues .