76908 - Vivado 2021.1 Vivado Versal Clocking : Deskew logic for MMCM and DPLL are timed incorrectly - In Versal devices, for the MMCM and DPLL, all outputs using the phase detector deskew logic (CLKIN_DESKEW, CLKFB_DESKEW ports) will be incorrectly timed in Vivado 2021.1.1 and earlier versions.

Release Date

2021-10-22