Solution - Solution

72992 - Design Advisory for Zynq UltraScale+ MPSoC/RFSoC: Possible link training failures or data errors on PCIe, SATA, or USB 3.0 protocol links using PS GTR

Release Date
2025-08-18
Revision
1.0 English

An updated fix is available in the REV4 patch for Vivado 2024.2 and earlier releases. No patch is required for Vivado 2025.1 or any subsequent releases, as all necessary fixes have been incorporated into the main release.

 

  • PCIe / USB 3.0 / SATA GEN2 / SATA GEN3
    • All customers are required to ensure that the REV4 patch is applied if they use the above protocols with the PS GTR. For Vivado versions where the patch is not available in this answer record, please contact support.

 


Note: 

  • After applying the patch you must use the reset project command in Vivado and rerun PCW on your Vivado design to enable the fix.
  • No hardware changes are made, so the bitstream does not need to be updated.
  • Embedded software must be rebuilt after running PCW to enable the fix. 
  • To verify that the patch has been applied correctly, make sure that the below text is included in your psu_init.c file.
    • static int serdes_illcalib

The below issues were found in the REV3 patch. These issues have been addressed in the current REV4 patch release.

 

  • Issue 1 - A write to OCM as part of the fix caused boot failures for some boot solutions. If this issue impacted your system, you will observe boot failures when loading the FSBL
  • Issue 2 - When SATA was used for certain configurations, link failures were observed. This was a functional issue with the patch where some incorrect settings were propagated and the SATA link would fail at boot.
  • Issue 3 - If there was a combination of PCIe and DisplayPort/USB/GEM or a combination of SATA and DisplayPort/USB/GEM, link failures could be observed on the DisplayPort, USB or GEM links. 
    The issue was caused by redundant PLL lock checks in the fix extending the calibration time and resulting in protocol timeouts.
    The following combinations are affected:

 

 At least one laneAt least one lane
CombinationPCIe or SATADisplayPort, USB, GEM


Users need to apply the REV4 patch with the AMD recommendations provided below:

 

  • Scenario 1 - User has not applied any fix for this issue
    • AMD Recommendation - For new designs and designs in Production, apply the attached REV4 patch for the relevant version of Vivado.
  • Scenario 2 - User has applied a previous version of the patch listed above and is impacted by any issue listed
    • AMD Recommendation - For new designs and designs in Production, apply the attached REV4 patch for the relevant version of Vivado.
  • Scenario 3 - User has applied a previous patch and is not impacted by the issues listed

    • AMD Recommendation - No update needed.

 

Known Issues:

Boot times are extended due to changes in the fix in configurations with both SATA and PCIe links. Boot time can increase by 200-300 ms for any configuration combining SATA and PCIe or where all four lanes are configured as PCIe.

AMD measurements were made on a system with the APU Clock running at max - 1200 MHz. For systems running a slower clock, the boot time might be greater than the above.


Additional System Considerations:

For all systems using SATA or PCIe, the GT Ref Clock must be present and stable from the beginning of the boot process.

This can have a similar failure mechanism to the issue described above. This requirement should also be checked. 

Link failures can be observed with and without the patch if this requirement is not met.

If your system cannot meet this requirement, please contact support.



Revision History:

12/20/2019Initial Release