In designs generated for Zynq UltraScale+ MPSoC/RFSoC devices in all versions of Vivado up to and including 2020.3, you might observe link training failures or data errors on PCIe, USB3.0, or SATA protocols when using PS GTR.
This article is part of the PCI Express Solution Centre
| (Xilinx Answer 34536) | Xilinx Solution Center for PCI Express |