Resource Utilization - 4.0 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)
Document ID
PG338
Release Date
2022-06-24
Version
4.0 English

The resource utilization of a sample DPUCZDX8G single core project is as follows. The data is based on the ZCU102 platform with low RAM usage, channel augmentation, alu parallel = PP/2, conv: leaky ReLU + ReLU6, alu: ReLU6 features, and high DSP usage.

Table 1. Resources of Different DPUCZDX8G Architectures
DPUCZDX8G Architecture LUT Register Block RAM DSP
B512 26391 34141 72 118
B800 28863 40724 90 166
B1024 33796 48144 104 230
B1152 31668 46938 121 222
B1600 37894 58914 126 326
B2304 41640 69180 165 438
B3136 45856 80325 208 566
B4096 51351 98818 255 710

Another example of a DPUCZDX8G single core project is based on the ZCU104 platform. In this project, the image and weights buffer utilize UltraRAM. The project is configured with low RAM usage, channel augmentation, alu parallel = PP/2, conv: leaky ReLU + ReLU6, alu: ReLU6 features, and high DSP usage. The resource utilization of this project is as follows.

Table 2. Resources of DPUCZDX8G using UltraRAM
DPUCZDX8G Architecture LUT Register Block RAM UltraRAM DSP
B512 26189 34172 0 18 118
B800 28878 40717 0 40 166
B1024 33532 48276 0 26 230
B1152 31102 46935 0 44 222
B1600 37463 59379 0 56 326
B2304 41192 69770 0 60 438
B3136 45481 80481 0 64 566
B4096 50904 98873 0 68 710