The DPUCZDX8G top-level interfaces are shown in the following figure.
Figure 1.
Two DPU Kernel Ports
The DPUCZDX8G I/O signals are listed and described in the table below.
| Signal Name | Interface Type | Width | I/O | Description |
|---|---|---|---|---|
| S_AXI | Memory mapped AXI slave interface | 32 | I/O | 32-bit memory mapped AXI interface for registers. |
| s_axi_aclk | Clock | 1 | I | AXI clock input for S_AXI |
| s_axi_aresetn | Reset | 1 | I | Active-Low reset for S_AXI |
| dpu_2x_clk | Clock | 1 | I | Input clock used for DSP blocks in the DPUCZDX8G. The frequency is twice that of m_axi_dpu_aclk. |
| dpu_2x_resetn | Reset | 1 | I | Active-Low reset for DSP blocks |
| m_axi_dpu_aclk | Clock | 1 | I | Input clock used for DPUCZDX8G general logic. |
| m_axi_dpu_aresetn | Reset | 1 | I | Active-Low reset for DPUCZDX8G general logic |
| DPUx_M_AXI_INSTR | Memory mapped AXI master interface | 32 | I/O | 32-bit memory mapped AXI interface for DPUCZDX8G instruction fetch. |
| DPUx_M_AXI_DATA0 | Memory mapped AXI master interface | 128 | I/O | 128-bit for Zynq UltraScale+ MPSoC series. |
| DPUx_M_AXI_DATA1 | Memory mapped AXI master interface | 128 | I/O | 128-bit for Zynq UltraScale+ MPSoC series. |
| dpux_interrupt | Interrupt | 1 | O | Active-High interrupt output from DPUCZDX8G. |
| SFM_M_AXI (optional) | Memory mapped AXI master interface | 128 | I/O | Memory-mapped AXI interface for softmax data. |
| sfm_interrupt (optional) | Interrupt | 1 | O | Active-High interrupt output from softmax module. |
| dpu_2x_clk_ce (optional) | Clock enable | 1 | O | Active-High clock-enable which is used to gate the 2x_clk input when clock gating is enabled. |
|
||||