AXI Master Interface - 3.3 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2023-05-16
Version
3.3 English

AXI4 (MM) Master ports are connected from the AMD Versal device Network on Chip (NoC) to the CPM DMA internally. For details, see Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313). The AXI4 Master interface can be connected to the DDR or the PL, depending on the NoC configuration.