The Vitis™ embedded software development flow has the following two methods to generate the core:
- GUI Flow
- Command Flow
It is recommended to use the command flow, as it is more convenient and flexible. If you want to use the GUI flow, see the tutorial here.
- Makefile and other scripts
- The DPU kernel is independently compiled to a Xilinx
object (.xo) file. It is compiled using
the package_xo utility. The RTL kernel wizard in the Vitis environment can
be used to simplify this process. The .xo file is linked with the hardware platform (shell) to
create the FPGA binary (.xclbin). The v++ compiler automatically uses the
Vivado® Design Suite tools to build
the kernels to run on the FPGA platform.
The Makefile and the other scripts are present in the Vitis DPU TRD.
- Configure DPU Parameters
- You can modify the Vitis-AI/DPU-TRD/prj/Vitis/dpu_conf.vh file to configure the DPU parameters. See Product Specification for more details on the DPU parameters.
- Architecture
- Select the DPU hardware architecture from the following:: B512, B800,
B1024, B1600, B2304, B3136, and B4096. For the B4096, the definition is as
follows:
`define B4096
- UltraRAM Number
- Modfiy the dpu_config.vh file to set
the numbers. Enable
`define URAM_ENABLE
and`define URAM_DISABLE
.When UltraRAM is enabled, set the following parameters:
-
'define def_UBANK_IMG_N 5
-
'define def_UBANK_WGT_N 17
-
'define def_UBANK_BIAS 1
There are some recommended UltraRAM numbers for different architectures. You can also adjust the numbers according to the resource usage of the entire project.Table 1. Recommended UltraRAM Numbers B512 B800 B1024 B1152 B1600 B2304 B3136 B4096 U_BANK_IMG 2 2 4 2 4 4 4 5 U_BANK_WGT 9 11 9 13 11 13 15 17 U_BANK_BIAS 1 1 1 1 1 1 1 1 -
- RAM Usage
-
RAM usage high -
`define RAM_USAGE_HIGH
RAM usage low -
`define RAM_USAGE_LOW
- Channel Augmentation
-
Enable -
`define CHANNEL_AUGMENTATION_ENABLE
Disable -
`define CHANNEL_AUGMENTATION_DISABLE
- DepthwiseConv
-
Enable -
`define DWCV_ENABLE
Disable -
`define DWCV_DSIABLE
- AveragePool
-
Enable -
`define POOL_AVG_ENABLE
Disable -
`define POOL_AVG_DISABLE
- Elementwise Multiply
-
Enable -
`define ELEW_MULT_ENABLE
Disable -
`define ELEW_MULT_DISABLE
- RELU Type
- There are four options of RELU type, they are:
- RELU_RELU6
- RELU_LEAKRELU_RELU6
If you want to use the RELU, LeakyReLU, and ReLU6, define as shown below:`define RELU_LEAKYRELU_RELU6
- DSP Usage
-
High -
`define DSP48_USAGE_HIGH
Low -
`define DSP48_USAGE_LOW
- Low Power Mode
-
Enable -
`define LOWPOWER_ENABLE
Disable -
`define LOWPOWER_DISABLE
- Device Configuration
-
Support Zynq UltraScale+ MPSoC -
`define MPSOC
Support Zynq-7000 devices -
`define ZYNQ7000
- Set the DPU Number
- The number of DPU cores is set to 1 by default. Add the [connectivity]
property to configure the DPU number as
follows:
[connectivity]
nk=dpu_xrt_top:2
The project will integrate two DPUs.
- Specify Connectivity for DPU Ports
- Specify the connectivity to the various ports in the system
for the DPU. Add the [connectivity] property to configure the DPU ports.Use the following command to check the ports of platform:
% platforminfo -p zcu102_base/zcu102_base.xpfm
If the platform does not have enough ports to connect to all the ports of the DPU, then the ports can be shared.
Add the [connectivity] property to specify the DPU ports as follows:
[connectivity]
sp=dpu_xrt_top_1.M_AXI_GP0:HP0
sp=dpu_xrt_top_1.M_AXI_HP0:HP1
sp=dpu_xrt_top_1.M_AXI_HP2:HP2
"
The project may have timing issues. You can add the [vivado]
property
to configure the Vivado implementation
strategy.
[vivado]
prop=run.impl_1.strategy=Performance_Explore
The Vivado implementation step uses the Performance_Explore strategy.