Revision History - 3.2 English

Control Interfaces and Processing System v3.2 LogiCORE IP Product Guide (PG352)

Document ID: PG352
Release Date: 2022-05-11
Version: 3.2 English

The following table shows the revision history for this document.

Section	Revision Summary
05/11/2022 Version 3.2
Design Flow Steps	Added SD Configuration section. Updated screens from CIPS 3.2. Updated XilSEM Library Configuration, Block Automation, System Monitor, and Boot Mode sections.
10/27/2021 Version 3.1
Design Flow Steps	Updated screens for CIPS 3.1.
Output Clocks	Added LPD Top switch clocking restriction.
AXI4 I/O Compliant Interfaces	Added ACE-Lite GUI information.
Boot Mode	Added `CONFIG.PS_PMC_CONFIG` parameter. Deleted `CONFIG.PS_USE_STARTUP` parameter.
Upgrading	Added appendix.
06/16/2021 Version 3.0
Design Flow Steps	Updated screens from CIPS 3.0. Added Choosing a Design Flow, CIPS Presets, and Power Configuration sections. Added support of CPM5.
Automation	Modified Board automation through Block automation. Added support of LPDDR in Block Automation.
Tamper Events/Response Configuration	Deleted Voltage Tamper event.
XilSEM Library Configuration	Modified content for detect and correct soft errors.
12/04/2020 Version 2.1
Initial release.	N/A