The following is the list of interfaces between PS/PMC and NoC. You can select these in the NoC interfaces section to communicate with the DDR/PL/AIE.
- Coherent (CCI) master ports
- The CIPS IP core has four coherent master ports (FPD_CCI_NOC_0,1,2,3) connected from PS-CCI to NoC. CCI drives these ports in interleaving mode (2 ports and 4 ports), so you must connect all 4 ports to NoC to access any slave. The CIPS core masters A72/R5/PMC/DMA can make use of these ports. Also, PL masters that are connected to CIPS on CCI slave ports can access these ports.
- Non-Coherent (NCI) master ports
- The CIPS core has two
non-Coherent master ports (FPD_AXI_NOC_0,1). Only PL masters which are connected
to NCI slave ports of the CIPS core can access these ports.Tip: Coherency is NOT enabled by default at boot on the CCI AXI-Lite ports.
- LPD (RPU) master port
- There is one master port from LPD (NOC_LPD_AXI_0) to NoC. LPD masters RPU/DMA can make use of this master port to access slaves.
- PMC master port
- The CIPS core has one master port (PMC_NOC_AXI_0) from PMC domain to NoC. This port is used by PMC for debug/boot.
- CPM4/5 master ports
- Two master ports (IF_PS_NOC_PCIE_0,1) are exposed from the CIPS core. One is connected to controller 0 and the other is to CCIX module. CPM4/5 can access DDR/PL/AIE regions using these ports. You can select connected ports in the CPM4/5 Configuration page.
- Coherent (CCI) Slave ports
- The CIPS core has two coherent slave ports (NOC_FPD_CCI_0,1). Masters connected to these ports can achieve coherency and virtualization. Masters connected to these ports can access DDR, PL slaves which are connected to CIPS via CCI ports. Also PL masters have access to CIPS internal memory regions.
- Non-Coherent (NCI) Slave ports
- The CIPS core has two non-coherent slave ports (NOC_FPD_AXI_0,1). Masters connected to these ports can achieve only virtualization. PL masters connected to these ports can access DDR, PL slaves which are connected to CIPS via NCI ports. Also PL masters have access to CIPS internal memory regions.
- PMC/LPD Slave port
- There is one slave port (NOC_PMC_AXI_0) to LPD/PMC region. PL masters connected to this port will get access to these regions.
- CPM4/5 Slave port
- The CIPS core has one NoC slave port (IF_NOC_PS_PCIE_0) connected to CPM4/5 module. External masters can connect to this port to configure the CPM4/5. You can select this port in the CPM4/5 Configuration page.
Figure 1 shows different NoC master/slave port options to enable these ports.
The following table shows the addresses you can assign to DDR/AI Engine/PL slaves which are connected to CIPS master NoC ports. For more information on NoC address ranges and configuration, see Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).
| Slave | Region | Start Address | Size |
|---|---|---|---|
| DDR | Low0 | 0x0 | 2 GB |
| Low1 | 0x800000000 | 32 GB | |
| Low2 | 0xC000000000 | 256 GB | |
| Low3 | 0x10000000000 | 734 GB | |
| CH1 | 0x50000000000 | 1 TB | |
| CH2 | 0x60000000000 | 1 TB | |
| CH3 | 0x70000000000 | 1 TB | |
| PL | PLNOC2 TB | 0x20100000000 | 2044 GB |
| PLNOC8 TB | 0x80000000000 | 8 TB | |
| AI Engine | AIE_0 | 0x20000000000 | 4 TB |
The following figures describe CIPS + DDR + PL slave connections on NoC:
Figure 1. CIPS NoC
Figure 2. NoC General Configuration
Figure 3. NoC Slave Ports Configuration
Figure 4. NoC Master Ports Configuration
Figure 5. NoC Connectivity Configuration