LUT_REMAP - 2023.1 English

The opt_design -remap option combines multiple LUTs into a single LUT to reduce the depth of the logic. Remap optimization can also combine LUTs that belong to different levels of the logical hierarchy.

Remapped logic is combined into the LUT that is furthest downstream in the logic cone.

The LUT_REMAP property lets you perform selective LUT remapping by applying the property to sequential LUT pairs to direct opt_design to merge them into a single LUT.

Chains of LUTs with LUT_REMAP properties are collapsed into fewer logic levels where possible.

Refer to the Vivado Design Suite User Guide: Implementation (UG904) for more information on optimization.

Architecture Support

All architectures.

Applicable Objects

LUT Cells (get_cells)

Values

• TRUE | 1
  • If opt_design -remap is called, the presence of the LUT_REMAP property with a value of TRUE has no additional effect.
  • If opt_design -remap is not called, the presence of the LUT_REMAP property with a value of TRUE on specific cells will call LUT remapping only for those specific cells during opt_design.
• FALSE | 0: This setting has no effect as it does not prevent the LUT from being remapped.

Syntax

Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax

set_property LUT_REMAP <value> <objects>

XDC Syntax Example:

The following assigns the LUT_REMAP property to the specified LUT primitives:

set_property LUT_REMAP 1 [get_cells usbEngine*/* -filter {ref_name =~ LUT*}]

Affected Steps

• Logic Optimization (Opt Design)