The CASCADE_HEIGHT attribute is an integer used to describe the length of the cascade chains of large RAMS that are put into block RAMs. When a RAM that is larger than a single block RAM is described, the Vivado synthesis tool determines how it must be configured.
Often, the tool chooses to cascade the block RAMs that it creates. This attribute can be used to shorten or limit the length of the chain. A value of 0 or 1 for this attribute effectively turns off any cascading of block RAMs.
This attribute can be placed on the RAM in question in the RTL source files, or in an XDC file, to drive synthesis.
Architecture Support
UltraScale and UltraScale+ architectures.
Applicable Objects
RAM Cells (get_cells)
Value
<VALUE>: Specify an integer.
Syntax
- VHDL Syntax
-
attribute cascade_height : integer; attribute cascade_height of ram : signal is 4; - Verilog Syntax
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(* cascade_height = 4 *) reg [31:0] ram [(2**15) - 1:0]; - XDC Syntax
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set_property CASCADE_HEIGHT 4 [get_cells my_RAM_reg]
Affected Steps
- Synthesis