Non-Project Mode Tcl Script Example - 2023.1 English

Vivado Design Suite User Guide: Design Flows Overview (UG892)

Document ID
Release Date
2023.1 English

The following example shows a Tcl script for the BFT sample design included with the Vivado Design Suite. This example shows how to use the design checkpoints for saving the database state at various stages of the flow and how to manually generate various reports. This example script, run_bft_kintex7_project.tcl, is available in the Vivado Design Suite installation at:


You can source the script from the Vivado Tcl shell, or the Tcl Console inside of the Vivado IDE.

# run_bft_kintex7_batch.tcl
# bft sample design 
# A Vivado script that demonstrates a very simple RTL-to-bitstream non-project batch flow
# NOTE:  typical usage would be "vivado -mode tcl -source run_bft_kintex7_batch.tcl" 
# STEP#0: define output directory area.
set outputDir ./Tutorial_Created_Data/bft_output             
file mkdir $outputDir
# STEP#1: setup design sources and constraints
read_vhdl -library bftLib [ glob ./Sources/hdl/bftLib/*.vhdl ]         
read_vhdl ./Sources/hdl/bft.vhdl
read_verilog  [ glob ./Sources/hdl/*.v ]
read_xdc ./Sources/bft_full_kintex7.xdc
# STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design
synth_design -top bft -part xc7k70tfbg484-2
write_checkpoint -force $outputDir/post_synth
report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
report_power -file $outputDir/post_synth_power.rpt
# STEP#3: run placement and logic optimzation, report utilization and timing estimates, write checkpoint design
write_checkpoint -force $outputDir/post_place
report_timing_summary -file $outputDir/post_place_timing_summary.rpt
# STEP#4: run router, report actual utilization and timing, write checkpoint design, run drc, write verilog and xdc out
write_checkpoint -force $outputDir/post_route
report_timing_summary -file $outputDir/post_route_timing_summary.rpt
report_timing -sort_by group -max_paths 100 -path_type summary -file $outputDir/post_route_timing.rpt
report_clock_utilization -file $outputDir/clock_util.rpt
report_utilization -file $outputDir/post_route_util.rpt
report_power -file $outputDir/post_route_power.rpt
report_drc -file $outputDir/post_imp_drc.rpt
write_verilog -force $outputDir/bft_impl_netlist.v
write_xdc -no_fixed_only -force $outputDir/bft_impl.xdc
# STEP#5: generate a bitstream
write_bitstream -force $outputDir/bft.bit