The Vivado Design Suite provides a Tcl command,
encrypt
, that performs encryption on IEEE-1735-2014 V2 valid
Verilog, SystemVerilog, and VHDL source files.
See this link in the Vivado Design Suite Tcl Command Reference Guide (UG835) for details.
The encrypt
command can also be used on the Verilog or VHDL output from
any stage of the Vivado tool flow.
The RTL source code can be encrypted, and then any files output by the
write_verilog
or write_vhdl
commands later in the
tool flow also have the protected IP automatically encrypted.