AMD Tool Rights - 2023.1 English

Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118)
Document ID
UG1118
Release Date
2023-05-30
Version
2023.1 English

AMD has created five specific tool rights that control Vivado tool behavior, as listed in the following table.

Table 1. AMD Specific Tool Rights
AMD Right Name Meaning AMD Valid Values Default Values
xilinx_configuration_visible Are the LUT values allowed to be visible in viewers, editors, and so forth, in Vivado? "true", "false" "false"
xilinx_enable_modification Can netlist information within the protected region (hierarchy, connections, LUTs, and so forth) be modified using the Vivado tool? "true", "false" "false"
xilinx_enable_probing Is the customer allowed to insert or instantiate Vivado debug probes in the protected region? "true", "false" "false"
xilinx_enable_netlist_export Is Vivado allowed to export a netlist of protected region? "true", "false" "true"
xilinx_enable_bitstream Is the Vivado tool allowed to write out a bitstream? "true", "false" "true"
xilinx_schematic_visibility Is Vivado allowed to show module names of the protected region in schematic or hierarchy viewer? "true", "false" "false" 1
  1. If xilinx_schematic_visibility right is not present in AMD toolblock, by default Vivado will hide module names inside the protected regions.
Important: IPs encrypted using 2018.3 or older version of Vivado, when used with 2019.1 or future versions, will not show module names due to the introduction of xilinx_schematic_visibility right. Update your IP and set this right to "true" to explicitly allow schematic visibility. Moreover, IPs encrypted with this right cannot be decrypted using 2018.3 or older version of Vivado.