Using Constraints Tutorial - 2022.2 English

Vivado Design Suite Tutorial: Using Constraints (UG945)

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2022.2 English
Important: This tutorial requires the use of the Kintex®-7 family of devices. You will need to update your Vivado® tools installation if you do not have this device family installed. Refer to the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973) for more information on Adding Design Tools or Devices.

This tutorial is comprised of two labs that demonstrate aspects of constraining a design in the Vivado® Design Suite. The constraints format supported by the Vivado® Design Suite is called Xilinx® Design Constraints (XDC), which is a combination of the industry standard Synopsys® Design Constraints and proprietary Xilinx® constraints. For more information on Timing Closure, see the UltraFast Design Methodology Timing Closure Quick Reference Guide (UG1292).

Video: You can also learn more about defining constraints in the Vivado Design Suite by viewing the quick take video at Vivado Design Constraints Overview.
Training: Xilinx provides training courses that can help you learn more about the concepts presented in this document. Use these links to explore related courses:

XDCs are not just simple strings; they are Tcl commands that the Vivado Tcl interpreter sequentially reads and parses. You can enter design constraints in several ways at different points in the design flow. You can store XDCs in one or more files that can be added to a constraint set in Vivado Project Mode, or read the same files directly into memory using the read_xdc command in Non-Project mode. For more information on Project and Non-Project modes, refer to the Vivado Design Suite User Guide: Design Flows Overview (UG892). With a design open in Vivado tools, you can also type constraints as commands directly in the Tcl Console when working in the Vivado IDE or at the Tcl command prompt when working outside of the IDE. This is particularly powerful for defining, validating, and debugging new constraints interactively in the design.

The Vivado Design Suite synthesis and implementation tools are timing driven. Having accurate and correct timing constraints is vital for meeting design goals and ensuring correct operation. Because the Vivado tools are timing driven, it is important to fully constrain a design, but not over-constrain, or under-constrain it. Over-constraining a design can lead to long compile times and sub-optimal results because the tool can struggle with unrealistic design objectives. Under-constraining a design can cause the Vivado tools to perform unnecessary optimizations, such as examining paths with multicycle delays or false paths, and prevent focus on the real critical paths.

This tutorial discusses different methods for defining and applying design constraints.