Debugging Flows - 2022.2 English

The Vivado tools provide several methods to add debug probes into your design. You need to determine which flow suits the requirements of your design. The available debug flows are:

• HDL instantiation debug probing flow: This flow involves explicitly adding debug IP cores into your HDL design, and attaching signals in the HDL source to an ILA debug probe.

  See this link to the Vivado Design Suite User Guide: Programming and Debugging (UG908) for more information on this flow.

  There are advantages and disadvantages to this flow, as follows:

  • Advantage: Provides the ability to probe at the HDL design level.
  • Disadvantages:
  • You must manually add and remove debug nets and IP in your design, by modifying your HDL source.
  • It is very easy to make mistakes when generating, instantiating, and connecting debug cores.
• Netlist insertion debug probing flow (Recommended): this flow involves explicitly attaching signals in the synthesized netlist to an ILA debug core instance:
  • Use the MARK_DEBUG attribute to mark signals for debug in the source RTL code.
  • Use the Mark Debug right-click menu option to select nets for debugging in the synthesized design netlist.

  The netlist insertion flow uses the Set up Debug wizard that guides you through the process of adding debug cores and probing signals of your design.

  • Advantages:
  • Most flexible with good predictability.
  • Allows probing at different design levels (HDL, synthesized design, system design).
  • Does not require HDL source modification.
  • Disadvantages: Cannot be used for IBERT or JTAG-to-AXI Master cores.
• Tcl-based netlist insertion flow: Use the set_property Tcl command to set the MARK_DEBUG property on debug nets, then use the following Tcl commands to add debug cores and probes to your synthesized design:
  • create_debug_core
  • create_debug_port
  • connect_debug_port