IP-Centric Design Flow - 2022.2 English

Vivado Design Suite User Guide: Designing with IP (UG896)
Document ID
UG896
Release Date
2022-11-02
Version
2022.2 English

The Xilinx® Vivado® Design Suite provides an intellectual property (IP) centric design flow that lets you add IP modules to your design from various design sources. Central to the environment is an extensible IP catalog that contains Xilinx-delivered Plug-and-Play IP. The IP catalog can be extended by adding the following:

  • Modules from System Generator for DSP designs ( MATLAB® from Simulink® algorithms)
  • Vivado High-Level Synthesis (HLS) designs (C/C++ algorithms)
  • Third-party IP
  • Designs packaged as IP using the Vivado IP packager tool

The following figure illustrates the IP-centric design flow.

Figure 1. IP-Centric Design Flow
Page-1 Sheet.98 Sheet.97 *SystemVerilog files must have a Verilog Wrapper. *SystemVerilog files must have a Verilog Wrapper. Sheet.96 Sheet.85 Sheet.86 Data store.64 Data store.65 Sheet.89 Data store.66 Sheet.91 Xilinx IP Xilinx IP Sheet.92 IP Catalog IP Catalog Sheet.93 3rd Party IP 3rd Party IP Sheet.94 User IP User IP Sheet.73 Sheet.21 Sheet.64 Process.26 Sheet.56 Sheet.42 X14070-030917 X14070-030917 Standard Arrow.519 Sheet.43 Process.507 Add Module Add Module Process.1 Document.23 Example Designs Example Designs Process.507 IP Packager IP Packager Document.512 RTL Source Files VHDL, Verilog, SystemVerilog*, (XCI/XCIX) RTL Source FilesVHDL, Verilog, SystemVerilog*, (XCI/XCIX) Document.21 Document Files Document Files Document.22 Simulation Model Files (simsets) Simulation Model Files (simsets) Document.24 Test Bench Test Bench Graphic ID: SW & IP Document.62 RTL IP Source Files VHDL, Verilog, SystemVerilog*, (XCI/XCIX) RTL IP Source FilesVHDL, Verilog, SystemVerilog*, (XCI/XCIX) Sheet.65 Sheet.72 Document.95 Block Design (BD) Block Design (BD)
Note: In some cases, third-party providers offer IP as synthesized EDIF netlists. You can load these files into a Vivado design using the Add Sources command.

The available methods to work with IP in a design are:

  • Use the Managed IP flow to customize IP and generate output products, including a synthesized design checkpoint (DCP) to preserve the customization for use in the current and future releases. See Using Manage IP Projects for more information.
  • Use IP in either Project or Non-Project modes by referencing the created Xilinx core instance (XCI) file, which is a recommended method for working with large projects with contributing team members.
  • Access the IP catalog from a project to customize and add IP to a design. Store the IP files either local to the project, or for projects with small team sizes, it is recommended that you save it externally from the project.
  • Add sources by right-clicking in IP integrator canvas and add an RTL module to a design diagram, which provides an RTL on Canvas. See this link to Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) for more information on module references.
  • Create and customize IP and generate output products in a Non-Project script flow, including generation of a DCP. See this link for more information about Non-Project mode in the Vivado Design Suite User Guide: Design Flows Overview (UG892).

    Always reference the IP using the XCI file. It is not recommended to read just the IP DCP file, either in a Project Mode or Non-Project Mode flow. While the DCP did contain constraints prior to 2017.1, in Vivado releases going forward, it does not contain constraints or provide other output products that an IP could deliver and that could be needed, such as ELF or COE files, and Tcl scripts.

The Vivado Design Suite Tutorial: Designing with IP (UG939) provides instruction on how to use Xilinx IP in Vivado.

Training: Xilinx provides training courses that can help you learn more about the concepts presented in this document. Use these links to explore related courses: Essentials of FPGA Design and Embedded Systems Software Design.