Step 3: Analyzing Output Bus Timing - 2022.1 English

Vivado Design Suite Tutorial: Implementation (UG986)
Document ID
UG986
Release Date
2022-05-24
Version
2022.1 English
Important: The tutorial design has an output data bus, wbOutputData, which feeds external logic. Your objective is to precisely control timing skew by manually routing the nets of this bus.

You can use the Report Datasheet command to analyze the current timing of members of the output bus, wbOutputData. The Report Datasheet command lets you analyze the timing of a group of ports with respect to a specific reference port.

  1. From the main menu, select Reports > Timing > Report Datasheet.
  2. Select the Groups tab in the Report Datasheet dialog box, as seen in the following figure, and enter the following:
    • Reference: [get_ports {wbOutputData[0]}]
    • Ports: [get_ports {wbOutputData[*]}]


  3. Click OK.

    In this case, you are examining the timing at the ports carrying the wbOutputData bus, relative to the first bit of the bus, wbOutputData[0]. This allows you to quickly determine the relative timing differences between the different bits of the bus.

  4. Click the Maximize button to maximize the Timing - Datasheet window and expand the results.
  5. Select the Max/Min Delays for Groups > Clocked by wbClk > wbOutputData[0] section, as seen in the following figure.

    You can see from the report that the timing skew across the wbOutputData bus varies by almost 660 ps. The goal is to minimize the skew across the bus to less than 100 ps.



  6. Click the Restore button so you can simultaneously see the Device window and the Timing - Datasheet results.
  7. Click the hyperlink for the Max Delay of the source wbOutputData[28].

    This highlights the path in the Device window that is currently open.

    Note: Ensure the Autofit Selection is highlighted in the Device window so you can see the entire path, as shown in the following figure.

  8. In the Device window, right-click on the highlighted path and select Schematic from the popup menu.

    This displays the schematic for the selected output data bus. From the schematic, you can see that the output port is directly driven from a register through an output buffer (OBUF).

    If you can consistently control the placement of the register with respect to the output pins on the bus and control the routing between registers and the outputs, you can minimize skew between the members of the output bus.



  9. Change to the Device window.

    To better visualize the placement of the registers and outputs, you can use the mark_objects command to mark them in the Device window.

  10. From the Tcl Console, type the following commands:
    mark_objects -color blue [get_ports wbOutputData[*]]
mark_objects -color red [get_cells wbOutputData_reg[*]]

    Blue diamond markers show on the output ports, and red diamond markers show on the registers feeding the outputs, as seen in the following figure.



    The outputs marked in blue are spread out along two banks on the left side starting with wbOutputData[0] (on the bottom) and ending with wbOutputData[31] (at the top), while the output registers marked in red are clustered close together on the right.

    To look at all of the routing from the registers to the outputs, you can use the highlight_objects Tcl command to highlight the nets.

  11. Type the following command at the Tcl prompt:
    highlight_objects -color yellow [get_nets -of [get_pins -of [get_cells \
wbOutputData_reg[*]] -filter DIRECTION==OUT]]

    This highlights all the nets connected to the output pins of the wbOutputData_reg[*] registers.

    In the Device window, you can see that there are various routing distances between the clustered output registers and the distributed outputs pads of the bus. Consistently placing the output registers in the slices next to each output port eliminates a majority of the variability in the clock-to-out delay of the wbOutputData bus.



  12. In the main toolbar, click the Unhighlight All button and the Unmark All button.