To create a project, use the New Project wizard to name the project, to add RTL source
files and constraints, and to specify the target device.
- Open the Vivado Design Suite integrated design environment (IDE).
- In the Getting Started page, click Create Project to open the New Project wizard.
- Click Next.
- In the Project Name page, do the following:
- Name the new project
project_ECO_lab
. - Provide the project location
C:/Vivado_Tutorial
. - Ensure that Create project subdirectory is selected.
- Click Next.
- Name the new project
- In the Project Type page, do the following:
- Specify the type of project to create as RTL Project.
- Leave the Do not specify sources at this time check box unchecked.
- Click Next.
- In the Add Sources page, do the following:
- Set the Target Language to Verilog.
- Click Add Files.
- In the Add Source Files dialog box, navigate to the /src/lab4 directory.
- Select all Verilog source files.
- Click OK.
- Verify that the files are added.
- Click Add Files.
- In the Add Source Files dialog box, navigate to the /src/lab4/IP directory.
- Select all of the XCI source files and click OK.
- Verify that the files are added and Copy sources into project is selected.
- Click Next.
- In the Add Constraints dialog box, do the following:
- Click the Add button , and then select Add Files.
- Navigate to the /src/lab4 directory and select ECO_kcu105.xdc.
- Click Next.
- In the Default Part page, do the following:
- Select Boards and then select Kintex-UltraScale KCU105 Evaluation Platform.
- Click Next.
- Review the New Project Summary page. Verify that the data appears as expected, per the steps above.
- Click Finish.Note: It might take a moment for the project to initialize.
- In the Sources window in the Vivado IDE,
expand top to see the source files for this lab.