Accessing Tcl Procs from an Installed App - 2022.1 English

Vivado Design Suite User Guide: Using Tcl Scripting (UG894)

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2022.1 English

Once you have installed an app, all the user procs that belong to this app can be accessed from the command line in two different ways:

  • From the ::<company>::<app> namespace. When Vivado IDE starts, a wrapper is automatically created for all the user procs for each installed app.
  • From the app full namespace qualifier ::tclapp::<company>::<app>, namespace in which the user proc has been defined.

For example, after the designutils app has been installed, the user proc, write_template, can be accessed with:

vivado% ::xilinx::designutils::write_template
vivado% ::tclapp::xilinx::designutils::write_template

The benefit of calling the proc from the ::xilinx namespace over the ::tclapp::xilinx namespace is that the wrapper that is created by Vivado supports a number of default command line arguments such as -help, -verbose, and -quiet, which are common to all built-in Vivado commands.

For example:

Vivado% xilinx::designutils::write_template -help
(User-written application)
Generates a Verilog/VHDL stub or instantiation template for the current design in 
memory (current_instance)
xilinx::designutils::write_template [-type <arg>] [-stub] [-template]
                                     [-language <arg>] [-verilog] [-vhdl]
                                     [-cell <arg>] [-file <arg>] [-append]
                                     [-return_string] [-usage] [-quiet]
template in the case of -return_string, otherwise 0 TCL_ERROR if error
  Name       Description
  [-type]      Type of template to create: stub or template
                    Default: stub
  [-stub]      Generate a stub (same as -type stub)
  [-template]    Generate a template (same as -type template)
  [-language]    Output language of the template: verilog or vhdl
                    Default: verilog
  [-verilog]    Verilog language (same as -language verilog)
  [-vhdl]      VHDL language (same as -language vhdl)
  [-cell]      Cell to generate template on. If not specified, runs on 
                    Default: current_instance
  [-file]      Output file name
                    Default: <module>.v or <module>.vhd
  [-append]     Append to file
  [-return_string] Return template as string
  [-usage]     Usage information
  [-quiet]     Ignore command errors
  [-verbose]    Suspend message limits during command execution
     Generates a Verilog/VHDL stub or instanciation template for the current design 
in memory (current_instance).
     This command must be run on a synthesized or implemented design.
::xilinx::designutils::write_template -verilog -return_string