SSI Technology Considerations for I/O Planning - 2022.1 English

Versal ACAP Board System Design Methodology Guide (UG1506)

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2022.1 English

When planning pinouts for an SSI Technology Versal device, it is important to recognize that XPIO banks are located in the bottom SLR (SLR0) instead of spread throughout the SLRs as in previous columnar architectures. In most cases, logic associated with an XPIO external interface must be located in the same SLR as the I/O and XPHY logic. In case the hardened DDR memory controller (DDRMC) is used, the associated data movement can be carried over the NoC and reach another SLR by leveraging the dedicated NoC routing without incurring additional PL design implementation complexity. When deciding on the placement of an external interface, considerations should include:

  • For smaller interfaces, group all pins within a single XPIO bank
  • For larger interfaces, group all pins in multiple adjacent XPIO banks
  • Place hardened DDR memory controllers in the corner banks that do not have PL access
  • Balance CCIO or CMT components across XPIO banks
  • For GT interfaces, group all GT pins within a minimal number of Quads
  • For GT interfaces connected to another hard IP (for example, PCIe, MRMAC, or DCMAC), keep all GT pins within the same SLR as the hard IP and on the same side of the SLR as the hard IP (left or right side), ideally in the same or adjacent clock region
  • For GT interfaces requiring access to MMCM or clock multiplexer resources, place the GT pins in the same SLR as the XPIO to reduce clock routing utilization