System Debug Planning - 2022.1 English

Versal ACAP System and Solution Planning Methodology Guide (UG1504)

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2022.1 English

The VersalĀ® ACAP includes a debug architecture that enables enhanced system debug methodology capabilities. This debug architecture is designed to work in any environment, including the lab, data center, and edge computing environments. For more information on debugging, see this link in the Versal ACAP System Integration and Validation Methodology Guide (UG1388).

The Versal ACAP debug architecture consists of a centralized debug packet controller (DPC), which is the packet processing engine of the debug architecture. The packets that are processed by the DPC are referred to as the debug and trace packets (DTP). These packets are decoded by the DPC to determine the commands, the destinations, and any potential higher-level flow control and management tasks. The DPC processes the DTP sent by a host, executes any commands embedded in the packets, and generates responses that are sent back to the host. For more information on the DPC, see this link in the Versal ACAP Technical Reference Manual (AM011).