Dataflow Simulation - 2022.1 English

Versal ACAP System and Solution Planning Methodology Guide (UG1504)

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2022.1 English

Dataflow simulation comprises performing systemC simulation for the NoC/DDR memory interface and accelerator hardware interface. You can use the Vitis™ hardware emulation flow to perform systemC simulation. The Vitis tools allow integration of the following into the platform, and automatically generate the test bench to run simulation:

  • Traffic model
  • Accelerator hardware
  • QEMU model to run processor code
  • Performance monitor blocks

You can tune the NoC and accelerator configuration based on the performance reported by monitor blocks. After the platform and accelerator tuning is complete, you can perform final verification with the actual traffic flow before running hardware validation.