IP-Generated Directories and Files

The following table lists the IP-generated target directories and files, which are also known as output products.

Xilinx recommends that you use Tcl commands to access the list of related files rather than using the file and directory structure view. For example, you can use the get_files Tcl commands, which are shown in Querying IP Customization Files. For more information, see the Vivado Design Suite Tcl Command Reference Guide (UG835).

Table 1. IP Output Products
Directory Name, File Name, or File Type	Description
`/doc`	Contains the `<Core_Name>` _changelog.txt file that provides information about changes to the IP for each release.
`/sim`	Contains the simulation sources files for IP. This directory is not present for all IP.
`/synth`	Contains synthesizeable source files for IP. This directory is not present for IP that does not support synthesis, such as simulation-only Verification IP.
<ip_name>.xci	Contains the IP customization information. You can generate the output products from this file. If an upgrade path exists for the IP in the Catalog, you can upgrade from this file to the latest version.
<ip_name>.xcix	Core Container file, which lists all the common elements between IP in a design.
<ip_name>.xml	IP Bill of Material (BOM) file that keeps track of the current state of the IP, including generated files, computed parameters, and interface information.
<ip_name>.veo\|vho	Verilog (VEO) or VHDL (VHO) instantiation template. You would use one of these files to instantiate the IP inside your design.
<ip_name>.dcp*	Synthesized Design Checkpoint file contains a post-synthesis netlist and processed XDC constraints. Xilinx recommends that you do not directly reference the IP DCP file; instead use the XCI file, which brings in the DCP when needed.
<ip_name>_stub.[v\|vhdl]*	Module (Verilog) and component (VHDL) for use with third-party synthesis tools to infer a black box for the IP.
<ip_name>_funcsim.[v\|vhdl]*	Post-synthesis structural simulation netlist files prior to Vivado release 2015.3.
<ip_name>_sim_netlist	Post-synthesis structural simulation netlist files in Vivado release 2015.3.
<ip_name>.xdc	Timing and/or physical constraints. These files are not present for all IP, and their location varies by IP.
<ip_name>_in_context.xdc	See Setting the Target Clock Period for more information.
dont_buffer.xdc	Deprecated file. Functionality is included in `<ip_name>_in_context.xdc`.
<ip_name>_clocks.xdc	Constraints with a clock dependency. These files are not present for all IP, and their location varies by IP.
<ip_name>_board.xdc	Constraints used in a platform board flow. These files are not present for all IP, and their location varies by IP.
<ip_name>_ooc.xdc	Default clock definitions used when synthesizing the IP out-of-context.
Encrypted HDL for the IP	Files used for synthesizing and simulating the IP. These files are not present for all IP, and their location varies by IP.
The DCP, `_stub`, and `_funcsim` or `_sim_netlist` files are created only when using the Out-of-Context flow for synthesis (default). See Synthesis Options for IP for more details.

Note: Although example design are not output products, they are commonly generated for IP. The example design files are only available when the example design is opened with one of the following:

In the Tcl Console, using the open_example_project command.
The Vivado IDE with the Open IP Example Design menu command.

For more information, see Using IP Example Designs.

IP-Generated Directories and Files - 2021.2 English

Vivado Design Suite User Guide : Designing with IP (UG896)